1. Technical Field
The present disclosure relates generally to semiconductor memories. More particularly, and not by way of any limitation, the present disclosure is directed to a system and method for peak current modeling for an integrated circuit (IC) design involving a compiler, e.g., a memory compiler.
2. Description of Related Art
Silicon manufacturing advances today allow true single-chip systems to be fabricated on a single die (i.e., System-On-Chip or SOC integration). However, there exists a “design gap” between today's electronic design automation (EDA) tools and the advances in silicon processes which recognizes that the available silicon real-estate has grown much faster than has designers' productivity, leading to underutilized silicon. Unfortunately, the trends are not encouraging: the “deep submicron” problems of non-convergent timing, complicated timing and extraction requirements, and other complex electrical effects are making silicon implementation harder. This is especially acute when one considers that various types of circuitry such as analog blocks, non-volatile memory (e.g., read-only memory or ROM), random access memories (RAMs), and other “non-logic” cells are being required. The gap in available silicon capacity versus design productivity means that without some fundamental change in methodology, it will take several staff years to develop leading-edge integrated circuits (ICs).
Design re-use has emerged as the key methodology solution for successfully addressing this time-to-market problem in semiconductor IC design. In this paradigm, instead of re-designing every part of every IC chip, engineers can re-use existing designs as much as possible and thus minimize the amount of new circuitry that must be created from scratch. It is commonly accepted in the semiconductor industry that one of the most prevalent and promising methods of design re-use is through what are known as Intellectual Property (“IP”) components—pre-implemented, re-usable modules of circuitry that can be quickly inserted and verified to create a single-chip system. Such re-usable IP components are typically provided as megacells, cores, macros, embedded memories through generators or memory compilers, et cetera.
It is well known that memory is a key technology driver for SOC design. It is also well known that obtaining accurate peak current estimates with respect to a memory instance is a major factor in designing high performance memories because of the requirement of adequate budgeting of an external decoupling or bypass capacitor that mitigates the parasitic inductive effects caused by the high frequency currents. Given that memories typically experience high current demands for only a short period of time due to simultaneous switching operations in the circuitry (thereby causing the parasitic voltages on the power supply lines), peak current demand requirements need to be estimated accurately as well as efficiently for a particular IC design. This is especially relevant where memory compilers have a wide range of memory configurations and peak current demands need to be estimated for each memory configuration.